Questions tagged [verilog]

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips.

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Should an output be output reg if using it in an instantiated sub module?

I'm trying to troubleshoot some code, which I might post later, but first I'm wondering if I need to change some of my module port definitions from simple outputs to output reg's? I know if I'm using ...
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17 views

Which tool I should use to create and simulate a C++ testbench? [on hold]

I am trying to create a C++ testbench against a Verilog RTL. I know that I need to use SV DPI to implement the same. Can anyone please tell me where can I simulate/run a C++ testbench? Will Visual ...
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2answers
20 views

shift left until MSB is 1: loop count limit exceeded. Condition is never false

I tried to shift left the "shifted register" until it's MSB is 1. But my code doesn't work. Compiler says "loop count limit exceeded. Condition is never false" input wire [31:0] targetnumber, ... reg ...
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1answer
24 views

How to capture keyboard input during runtime in Verilog?

I've been trying to find a way to capture keyboard input during runtime simulation of my Verilog code. Is this even possible? I have taken a look at resources like asic-world and the Quick Reference ...
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1answer
24 views

Add functional coverage to signal with condition

I'm new to functional coverage in system-verilog. I want to write a covergroup when two signal are not equal. For example, I have two separate coverages for each signal. covergroup group1 @(...
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1answer
18 views

Verilog - Is it possible to assign values to a register based on the genvar variables in a generate block

I have some code similar to this (one below is an example): genvar x; genvar y; generate for (y = -off; y < off; y=y+1) begin for (x = -off; x < off; x=x+1) begin ...
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1answer
33 views

Why is my 'data' register variable resetting to 0 once testbench gets into the fr_count conditional block?

Here is my module in question, and when I set my break point to the first line under (if fr_count == 20million), I can scroll over the 'data' register and 'data_store' register and they both read as 0....
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1answer
17 views

How to fix 'unknown module type error' when i run the verilog in terminal

when I run the Verilog code in terminal and it says there is an error in the first line of my code. and I don't know what is the problem.. when i run in the terminal it shows... num_7seg_B.v:2: ...
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2answers
44 views

Instantaneous module does not perform subtraction properly

I am trying to perform subtraction when ALX is 1 and ALY is 0 using instantaneous carry look ahead adder but it does not work properly. It works fine for addition. if ALX is 0 and ALY is also 0 it ...
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1answer
38 views

what $finish will be sythesis to in verilog?

For the digital computer, there always has a halt mode which basically mean to turn off the system. In the verilog, a $finish is used in verilog code. I am just wondering how the synthesizer will ...
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1answer
20 views

How to save data using $fwrite() command from verilog test bench such that the values of the multiple outputs save in adjacent columns of a csv file?

I am trying to write 256 different outputs of a verilog module through testbench using $fwrite() command. I do not know how to save these 256 outputs in 256 colums. If there's an option to put ...
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1answer
29 views

No warning concerning port and assignment in Questa 10.7b

I have a simple code: module test ( input a, output b ); assign a=0; assign b=0; endmodule As you can see a is input, which assigned, thats wrong.. but no warning is shown; my ...
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1answer
22 views

Pass Information From System verilog Testbench to a C++ Program Using pipes

I want to be able to pass information from System Verilog testbench to a c++ program through a pipe. Is there a way to implement this.
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1answer
20 views

UVM indexing into array by get_type_name

Is this possible? Get_type_name is a string. Can't I have an int array and use the name to index in? I get index expression type of illegal. Obj n1; int number[100]; n1 = new(); number[n1....
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1answer
30 views

How to use/call other modules? Implement own NAND Gate

I want to write my own NAND_GATE using my own AND_GATE module: module and_gate(input a, input b, output out); assign out = a & b; endmodule Method 1 What I came up with: module nand_gate(...
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1answer
39 views

Why won't === work when I compare a bit to 1'bx in iverilog?

I am trying to setup my test-bench for iverilog so that whenever some error bit is set to "x", the module will set some string called 'state_string' to 'START', and set 'state_string' to some other ...
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0answers
30 views

Can't change the inputs in initial Block of testbench

I'm new to verilog and I'm trying to write a simple testbench for a FSM. But I can't change the inputs in initial block. Reset should be 0 firstly then it should be 1 after 30ns. But reset is always ...
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0answers
29 views

result get changed when instantiate a submodule in some top module [closed]

I have a module which computes square of a number and it takes 10 clock cycles to compute the square. When I simulate the sqaure standalone using a test bench and provide the input number from test ...
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0answers
17 views

How to simulate FIR Compiler II in Quartus and ModelSim, ModelSim reports vlog-7

I called the FIR II core, full compilation can not be simulated, the ModelSim report the error(vlog -7), how can I solve this problem. I use the Quartus 18.0 and ModelSim 10.5b. # vlog -...
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1answer
27 views

Why there is a dely between 2 memory block of the while accesing?

I am building a Modulo reduction module for the Elleptic Curve Crypto System. I want to access the Ram such that 2 address is read in 2 clock pulses. but my code is giving a lag such that it is ...
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0answers
18 views

Xilinx Isim fatal error at combinational logic statement

I want to assign a value into a register do_jump to check whether an instruction requires a jump or not using a variable branch which holds some macro values. branch_condition is a register which ...
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0answers
44 views

Allow extern “C” function to call class member function [duplicate]

I have a verilog design that has DPI callbacks to some c++ code to service memory requests for my design. I need to have this DPI function to have access to the members of that class. Currently I have ...
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0answers
18 views

Will the following code synthesize into block RAM or distributed RAM on FPGA

Here , columns is a reg declared in the following way : reg [1022:0] columns [0:1022] ; always@(posedge S_AXI_ACLK) begin if(start_decoding == 1'b1) begin for(ii = 0 ; ii &...
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31 views

Trouble with implementing Boolean Function in ModelSim with Verilog

I'm looking to implement Y = (~A & ~B & C) | (A & ~B & ~C) | (~A & B & ~C) within ModelSim 10.7b. The following is what I have in ModelSim. boolean_function.v `timescale 1ns/...
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Datapath wiring in Verilog

I am developing an 8-bit microprocessor. I have developed all individual behavioral modules. Now while connecting them, I am just trying to integrate register memory first with the datapath. If I ...
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0answers
45 views

What is the correct way to access ROM: 1-Port

Instead of using $readmemh to read various large files / place the data into 16bit registers (which is using most of my logic elements), I am trying to find out how to access the ROM memory to display ...
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1answer
49 views

How to find middle point between 2 pulses in Verilog in an FPGA?

I'm trying to find the mid-point between hsync pulses in a video stream. There are many "pixel clocks" in between hsync pulses. How can I get a pulse or signal exactly at the midpoint between two ...
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1answer
28 views

Finding columns in a 2-D array in Verilog

I have a following code : `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 04/07/2019 01:20:06 ...
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2answers
45 views

What is the best way to detect pulses between two clock domains?

I want to transfer a pulse from a clock domain clk1 to another clock domain clk2, but we don't know which one is faster than the other! What is the best way to do that? Thanks,
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1answer
24 views

How does “if” work with registers in verilog?

a = reg[3:0]. what values of "a" return true in: "if(a)"?. which cell of the register a does the "if" check in the previous format?. Does it return 0 only for a=0000 or are there other values for a ...
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1answer
27 views

How can I figure out bit/byte size?

I'm confused by bit/byte. I know that 8bit is equal to 1byte. Then, in Verilog, if inputs are defined as input [31:0] start; input [31:0] end; What are the bit sizes and byte sizes of these? ...
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0answers
19 views

How to design iteration in combination circuit

I am design a floating adder using combination circuit in Verilog There are five steps: compare exponents -> shift smaller number right -> Add -> normalize -> round When I finish Add step and get ...
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1answer
26 views

Passing by reference into System Verilog module or Interface

I would like to create a reusable interface or module where the hierarchy of a memory element outside it can be passed to it by reference. I know passing by reference cannot be done to a module or an ...
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0answers
31 views

How to pass a SystemVerilog struct containing a dynamic array via DPI-C?

Here is a minimal working example of the problem: Below example compiles fine (using Cadence Incisive/Xcelium) if I comment out the import "DPI-C" statement and the call to print_object(s);. So that ...
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2answers
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How to iterate all argument passed to a task or function in SV?

It is possible to iterate through all the argument that I passed to a system verilog task or function such as argv in c and @ARGV in Perl? Since I don't have any idea of how many argument that are ...
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0answers
44 views

Data is not going into memory

enter image description hereI am trying to implement memory read write operation. On clk_1,it insert data in memory but it's not getting stored in memory. Can you please help with that? Dut: module ...
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0answers
27 views

Sending out a signal using AXI registers with Verilog

I need to send out a signal using a board which includes a Zynq. I have created a custom AXI peripheral which has several out ports that I have so defined: output reg clk_out, output reg signal_1, ...
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2answers
47 views

Using SystemVerilog structs that contain parameters as input/output ports to a module

My struct contains parameters that vary per module. I'd like to use this struct to pass input/outputs to these modules. I'm using this for design so it has to be synthesizable and my toolchain doesn't ...
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1answer
32 views

How to do a logical operation per instance in a vector of instances

Say I have a module with inputs of N bits and a single bit that I instantiate like so: module foo ( input wire [N-1:0] x, input wire y ); foo u__foo ( .x(x), .y(x == something) ); And ...
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1answer
36 views

Add delay between sampling and checking

I have written an assertion property. I want to add delay between sampling and checking action. Basically below assertion says that assert_sig should be stable when sig1 or sig2 1. property ...
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1answer
24 views

Register type variable gives error : unknown type

I'm making a 1 bit positive edge Dflipflop. All outputs should be assigned only when there is a positive edge of the clock signal. Q is same as D, Qbar is the negation of D. It somehow works when I ...
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1answer
34 views

Vivado Behavioral Simulations showing undefined (XX) output

I'm attempting to run a behavioral simulation on my Verilog code in Vivado, however after the simulation runs instead of getting outputs, they are shown as Red lines with XX, which I believe means ...
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1answer
32 views

“Syntax in assignment statement l-value” Why is this code not compiling?

module FiniteStateMachine(output reg [2:0] Count, input clock, reset); reg[2:0] state, next_state; parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101, S6 = 3'b110, ...
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1answer
27 views

Why are the outputs not changing/not getting loaded in my single cycle architecture implementation?

I've written the code for the single cycle MIPS Architecture which implements add, sub, multiply and divide. There's a 2D Reg array, A control unit, an ALU. I think I've written it all right but the ...
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0answers
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Would this design be considered an FIR filter?

If you added registers, or delays, in parallel to the registers shown in the diagram, would that be considered an FIR filter? In this case, it would be adding 4 additional registers: 1 between the ...
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1answer
45 views

Priority case with for loop inside always_comb Procedural block gives error?

I am trying to build a static priority encoder, for example, 0011101010------>0010000000 Basically the index with highest value should be one and other indices must be zero. I have tried the ...
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1answer
23 views

How to apply stimulus to an array through a testbench

I want to apply some values to input "in " through the testbench . Tb part is attached below , I know it is wrong, how can one do this in verilog ? reg clk; reg reset; reg [size-1:0] in[elements_num-...
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Not able to run and get outputs

The challenge is to write a verilog code for a circuit which first adds any two 12bit integers and compares this sum with a third 12bit integer and shows the greater one among them as the final output ...
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1answer
30 views

What does this verilog assign function do?

If sig_in = 0000, 0001, 0010, ... ,1111 sig_out = {sig_in[3], sig_in[3], sig_in[3: 2]}; If I'm reading this right, sig_out[3] will be sig_in[3], sig_out[2] will also be sig_in[3], and I'm not sure ...
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Changing ASM into control unit and data path

I am trying to change my pig game from simple ASM chart to one where where i can have control unit and data path I made an ASM chart for the pig game that shows how my program works I expect the ...

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